This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-153885, filed on May 28, 2002, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a signal transmission technology for enabling high-speed signal transmission between a plurality of LSI chips or a plurality of devices or circuit blocks within a single chip, or between a plurality of boards or cabinets, and more particularly to an output circuit device to be used for clock signal distribution in high-speed signal transmission, and a system constructed with such output circuit devices.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of processors and semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories). The improvements in the performance of semiconductor memory devices, processors, etc. have reached the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
Specifically, the speed gap between a memory such as a SRAM or DRAM and a processor (i.e., between LSIS), for example, has been widening, and in recent years, this speed gap has been becoming a bottleneck in a computer""s performance. Further, not only the speed of signal transmission between such chips, but because of increasing integration and increasing size of chips, decreasing supply voltage levels (decreasing signal amplitude levels), etc. the speed of signal transmission between elements or circuit blocks within a single chip is also becoming a major factor limiting the performance of the chip. Moreover, the speed of signal transmission between a peripheral device and the processor/chipset also is becoming a major factor limiting the overall performance of the system.
Here, a technique for distributing a clock for accurate timing becomes important when it comes to increasing the speed of signal transmission within a cabinet or between circuit blocks or chips. That is, as the timing accuracy of the distributed clock directly affects the accuracy of receive timing and also the timing accuracy of a signal to be generated, a buffer that can minimize the occurrence of jitter must be used as a clock buffer for clock distribution. This applies not only to the clock distribution buffer, but also to various other output circuit devices that are required to operate at high speed with accurate timing.
In the prior art, it was difficult to provide an output circuit device that can operate at high speed with accurate timing by minimizing the occurrence of jitter.
The prior art and its associated problem will be described in detail later with reference to relevant drawings.
An object of the present invention is to provide an output circuit device that can operate at high speed with accurate timing by minimizing the occurrence of jitter.
According to the present invention, there is provided an output circuit device comprising an output circuit connected between a first power supply line and a second power supply line via a control circuit having at least one isolating transistor, wherein a control voltage held at a constant level is applied to a control electrode of the isolating transistor, and the control voltage is a voltage at a level that works to attenuate high-frequency components contained in a voltage supplied from the first or the second power supply line.
Further, according to the present invention, there is also provided an output circuit system having a plurality of output circuit devices, multi-phase clocks being transmitted through the plurality of output circuit devices, and phase spacing between multiple phases being maintained constant by adjusting the amount of delay in each of the output circuit devices in accordance with an output of a uniformity detection circuit that detects phase uniformity between the multi-phase clocks, wherein each of the output circuit devices comprises an output circuit connected between a first power supply line and a second power supply line via a control circuit having at least one isolating transistor, wherein a control voltage held at a constant level is applied to a control electrode of the isolating transistor, and the control voltage is a voltage at a level that works to attenuate high-frequency components contained in a voltage supplied from the first or the second power supply line.
The control circuit may comprise a high-frequency component attenuating capacitor one end of which is connected to the control electrode of the isolating transistor. The isolating transistor may be a source-grounded MOS transistor, and the other end of the high-frequency component attenuating capacitor may be connected to a source side of the first or the second power supply line whichever is connected to the source-grounded MOS transistor. The isolating transistor may be a pMOS transistor whose source is connected to the first power supply line, and whose drain is connected to the output circuit, and the other end of the high-frequency component attenuating capacitor may be connected to the first power supply line. The isolating transistor may be an nMOS transistor whose source is connected to the second power supply line, and whose drain is connected to the output circuit, and the other end of the high-frequency component attenuating capacitor may be connected to the second power supply line.
The isolating transistor may be a source-follower connected MOS transistor, and the other end of the high-frequency component attenuating capacitor may be connected either to the first or the second power supply line whichever is not connected to the source-follower connected MOS transistor, or to a node having a prescribed potential difference relative to the power supply line not connected to the source-follower connected MOS transistor. The isolating transistor may be an nMOS transistor whose source is connected to the output circuit, and whose drain is connected to the first power supply line, and the other end of the high-frequency component attenuating capacitor may be connected to the second power supply line. The isolating transistor may be a pMOS transistor whose source is connected to the output circuit, and whose drain is connected to the second power supply line, and the other end of the high-frequency component attenuating capacitor may be connected to the first power supply line.
The control voltage may be generated through a noise reduction filter circuit, and the noise reduction filter circuit may attenuate the high-frequency components contained in the voltage supplied from the first or the second power supply line whichever is connected to the isolating MOS transistor. The output circuit may comprise a pair of inverters amplifying differential signals, and a voltage passed through the control circuit may be applied to a back gate of a transistor forming each of the inverters. A well of each pMOS transistor forming the pair of inverters may be connected to the source of the pMOS transistor.
The isolating transistor may be provided on at least one side, either between the output circuit and the first power supply line, or between the output circuit and the second power supply line. The isolating transistor may be provided on both sides, both between the output circuit and the first power supply line and between the output circuit and the second power supply line.
The output circuit device may further comprise a low-pass filter circuit provided in series to the isolating transistor. The low-pass filter circuit may comprise a filter transistor connected in series between the isolating transistor and the first or the second power supply line; and a filter capacitor one end of which is connected to a connection node between the isolating transistor and the filter transistor. A potential on the first or the second power supply line, whichever is not connected to the filter transistor, may be applied to a control electrode of the filter transistor as well as to the other end of the filter capacitor.
The low-pass filter circuit may comprise a filter resistor connected in series between the isolating transistor and the first or the second power supply line; and a filter capacitor one end of which is connected to a connection node between the isolating transistor and the filter resistor. A potential on the first or the second power supply line, whichever is not connected to the filter resistor, may be applied to the other end of the filter capacitor.
According to the present invention, there is provided an output circuit device comprising an amplifier circuit to which an input signal is supplied, wherein a common-mode voltage of the input signal is adjusted to a value substantially equal to a common-mode voltage of an output signal output from the amplifier circuit.
Further, according to the present invention, there is also provided an output circuit system having a plurality of output circuit devices, multi-phase clocks being transmitted through the plurality of output circuit devices, and phase spacing between multiple phases being maintained constant by adjusting the amount of delay in each of the output circuit devices in accordance with an output of a uniformity detection circuit that detects phase uniformity between the multi-phase clocks, wherein each of the output circuit devices comprises an amplifier circuit to which an input signal is supplied, wherein a common-mode voltage of the input signal is adjusted to a value substantially equal to a common-mode voltage of an output signal output from the amplifier circuit.
The adjustment of the common-mode voltage of the input signal may be performed by a common-mode feedback circuit provided on an output side of a transmitting circuit that transmits signals to the output circuit device. The adjustment of the common-mode voltage of the input signal may be performed by terminating the input signal with a power supply that is provided on an input side of the output circuit device and that generates a common-mode voltage of a prescribed level. The adjustment of the common-mode voltage of the input signal may be performed by capacitively coupling the input signal with the amplifier circuit and by supplying a DC potential, after the capacitively coupling, to a power supply that is provided on an input side of the output circuit device and that generates a common-mode voltage of a prescribed level.
The output circuit device may further comprise a duty detection circuit detecting an output duty of the output circuit; and a duty adjusting circuit adjusting the output duty of the output circuit in accordance with the detected duty, and wherein the ratio of the output duty is controlled to approximately 50%. The output circuit device may be a clock buffer used for clock signal distribution.